1. Field of the Invention
The invention relates to a method for manufacturing multilevel interconnects, and in particular to a method for manufacturing a dual damascene structure.
2. Description of the Prior Art
In a traditional method for manufacturing interconnects, an insulating layer, such as a silicon oxide layer, is used to isolate two patterned metal layers formed on both surfaces thereof from each other. Furthermore, via holes are formed between the patterned metal layers in the insulating layer, wherein the via holes are filled with conductive layers having material similar to or even completely different from the patterned metal layers, thereby vertically and electrically connecting the patterned metal layers. It is noted that designs having more than two metal layers are increasingly adopted in IC manufacture in line with miniaturization of ICs. Generally, the insulating layer isolating the patterned metal layers from each other is called an intermetal dielectric (IMD) layer, and the conductive layers formed inside the via holes for vertically connecting the patterned metals are called vias.
Typically, there are two prior methods for manufacturing via holes and interconnects. In the first method, an inter-metal dielectric layer is formed on a first patterned metal layer. Then, via holes are formed in the dielectric layer by photolithography and etching. Next, conductive layers, serving as vias, are formed in the via holes by deposition. Finally, a second patterned metal layer is formed on the inter-metal dielectric layer and the vias.
The other method introduces a dual damascene technique in which via holes and interconnects are formed simultaneously.
In the dual damascene technique, an insulating layer is formed on a substrate, and then planarized. Thereafter, the insulating layer is etched to form trenches and via holes based on the required pattern of a subsequently formed metal line. That is, the insulating layer is etched to form the trenches for use of subsequently formed metal lines, while also being etched, until active regions or connections in the substrate are exposed, to form the via holes. Then, a metal layer is deposited in the trenches and the via holes to form the metal lines and vias, respectively. Finally, chemical mechanical polishing (CMP) is performed for planarization. The steps described above are repeated, thereby forming another dual damascene structure.
To illustrate a method employed in the prior art, reference is made to FIGS. 1A-G. FIG. 1A shows a substrate 100 with a flat surface provided (devices formed in the substrate 100 are not shown). A conductive layer (not shown) is formed on the substrate 100 and then patterned to form metal lines 102a. 102b and 102c by photolithography and etching. At the same time, portions of the substrate 100 surface are exposed.
Referring to FIG. 1B, a first dielectric layer 104, such as a silicon oxide layer, is deposited on the substrate 100 by chemical vapor deposition (CVD). Next, the first dielectric layer 104 is polished by chemical mechanical polishing until the surfaces of the metal lines 102a, 102b and 102c are exposed.
Referring to FIG. 1C, a second dielectric layer 106, such as a silicon oxide layer, is deposited on the metal lines 102a, 102b and 102c and the first dielectric layer 104 by chemical vapor deposition, and then is planarized. The thickness of the second dielectric layer 106 is approximately equal to the depth of each subsequently formed via. Thereafter, an etching stop layer 108, such as a silicon nitride layer, is formed on the second dielectric layer 106 by chemical vapor deposition.
Referring to FIG. 1D, an opening 110 is formed in the etching stop layer 108 by photolithography and etching, such as reactive ion etching (RIE), and a portion of the second dielectric layer 106 surface is concurrently exposed. The opening 110 is directly above the metal line 102b.
As shown in FIG. 1E, a third dielectric layer 116, such as a silicon oxide layer, is formed on the etching stop layer 108 and in the opening 110 by chemical vapor deposition, and then is planarized until the thickness of the third dielectric layer 116 is approximately equal to the required depth of a subsequently-formed trench.
Referring to FIG. 1F, the third dielectric layer 116 is etched to form a trench 118a by photolithography and etching, such as reactive ion etching (RIE). Then, the third dielectric layer 106 is continuously etched until the surface of the metal line 102b is exposed, forming a via hole 118b below part of the trench 118a. In other words, due to the existence of the etching stop layer 108, a larger opening 118 formed for use in manufacturing a dual damascene structure includes the opening 118a and the via hole 118b, wherein the upper part of the larger opening 118 is wider than the lower part of the larger opening 118.
Referring to FIG. 1G, a conductive layer (not shown) is formed on the third dielectric layer 116 and in the trench 118a and the via hole 118b, and then is polished by chemical mechanical polishing until the surface of the dielectric layer 116a is exposed. As a result, a conductive line 122 is formed.
As described above the prior method for manufacturing a dual damascene structure involves a relatively complicated set of steps to form the tapered opening 118. In short, the prior method has the disadvantages of requiring an excessive number of inter-metal dielectric depositions and depositing at least one layer of etching stop. Therefore, the prior method needs more deposition steps, resulting in higher costs and greater time consumption. In addition, it is easy to cause misalignment when forming via holes by photolithography and etching.